Design of Digit Serial FIR Filter
Prof. Abhijit Gajendra Kalbande
Assistant Professor
Prof Ram Meghe College of Engineering & Management, Badnera-Amravati
abhijit.g.kalbande@gmail.com
Dr.Saurabh Ashok Ghogare
Assistant Professor,
Adarsha Science J.B.Arts& Birla commerce Mahavidyalaya Dhamangaon Rly.
saurabh.a.ghogare@gmail.com
Abstract- Today filter is the most important component in digital signal processing system from last few decade, on low complexity bit-parallel multiple constant multiplication (MCM) more efficient algorithm and architecture has been developed which are used in DSP system but it offer more complexity as compared to digit serial MCM filter due to which we are interested in design of digit serial MCM filter it has low cost and offers more delay. In this paper we address more the problem of optimizing the area required for to design filter and also we introduce high level synthesis algorithm and overall design architecture. In that experimental result of digit serial FIR MCM filter will be given in term of the area, delay and power efficiency for different algorithm and architecture.
Keywords: –integer linear programming (ILP), digit serial arithmetic, finite impulse response ((FIR) filters, gate level area optimization, multiple constant multiplication.
DOI link – https://doi.org/10.69758/GIMRJ/2504I5VXIIIP0001
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